1. Field of Invention
This invention relates generally to read only memories and more particularly to an electronically programmable read only memory of high integration density which is capable of high speed operation.
2. Prior Art
Read only memories (ROMs) are widely used in data processing equipment. Generally, ROMs are used to constitute tables containing fixed data intended only to be read in the course of equipment operation. ROMs, for example, are used to hold the data words which control the instructions of a program in a computer control unit or a microprocessor. Additionally, ROMs may be used to form the AND and OR matrices of a programmable logic array (PLAs).
In these applications, it is desirable for the ROM to operate at the highest possible speed and in fact a speed substantially equal to the operating speed of the random access memories (RAMs) which contains the variable data the ROM data will be associated with during equipment operation. In addition, it is desirable for the programming operation required to load data in a ROM to be as simple as possible to retain the ROM's desirability of use.
Currently, there are various types of ROMs. For example, there are ROMs which are programmed during manufacturing. These ROMs have a high integration density obtained by making the ROM as an array of cells, each cell having only one bipolar transistor. The cells are personalized, i.e., loaded with a "0"'s and "1"'s pattern when made by providing an open circuit (0) or not providing an open circuit (1) at the cell transistor's emitter. This type ROM exhibits high operating speed and integration density but unfortunately cannot be personalized, i.e., programmed, by the user.
There are also ROMs which can be electrically programmed, i.e., programmable read only memories (PROMs) which may be personalized by the user. An example of such a ROM is a structure that features floating gate CMOS transistors as described in the article entitled "Single-Supply Erasable PROM Saves Power with C-MOS Process" appearing in the July 6, 1978 issue of the publication Electronics at pages 106-111. This type of device, however, does not operate at a speed high enough to satisfy the needs of many potential users.
Generally, user programmable ROMs having high operating speed, e.g., 5 to 10 ns access/cycle time feature a matrix of memory cells, each of which includes a bipolar transistor having a fusable resistor connected to the transistor emitter. In this arrangement, the resistor is fused open or left intact to establish either a "0" or "1" binary level in the cell. Typically, the user fuses the resistor open by driving a high current through it.
Such memories are described in the article entitled "Bipolar PROM Reliability" which appears in the publication Micro Electronics Reliability Vol. 18 at pages 325 to 332, Paragon Press. Unfortunately, in this type of PROM, the fusable resistor requires an undesirably large amount of space and, therefore, does not permit the component integration density desired.
There are also PROMs in which a dielectric is placed in series with the cell transistor emitter and either left intact to program a "0" at the cell or broken down by the application of a high voltage to program a "1" in the cell. An example of this type of PROM is found in U.S. Pat. No. 3,576,549, issued to Hess et al. PROMs of this type, however, use a high dielectric strength material, for example, silicon dioxide, alumina, silicon nitride, etc. Therefore, for the dielectric thicknesses which can be readily achieved, these layers have high breakdown voltages, e.g., 5 to 100 v. Such voltages unfortunately create difficulty in high integration density circuits and make programming of the PROM by the user inconvenient.
It has been possible to achieve high speed at high integration density in certain types of dynamic RAMs. Particularly where a capacitor is connected to the emitter of a bipolar transistor, a binary "1" or "0" may be represented by charging or not charging the capacitor. Such an arrangement is described in U.S. Pat. Nos. 3,979,734 and 3,876,944 respectively entitled "Multiple Emitter Charge Storage Memory Cell" and "Dibinary Encoding Technique" issued to W. D. Pricer et al and D. E. Mack et al on Sept. 7, 1976 and Apr. 8, 1975. Unfortunately, however, because the capacitor charge is volatile, i.e., it requires refreshing, such a structure is unsuited for a ROM which must maintain the information loaded into it.